Regviz

Freescale Semiconductor /MKE14D7 /PDB2 /CHDLY2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CHDLY2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKE14D7/PDB3/CHDLY2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLY0RESERVED

Description

Channel n Delay 2 Register

Fields

DLY

PDB Channel Delay
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data